1. Field
The present disclosure relates generally to phase locked loops (PLL), and in particular, to a system and method of controlling power consumption in a digital phase locked loop (DPLL).
2. Background
Communication devices typically include a local oscillator (LO) for synchronously transmitting and receiving signals to and from other remote communication devices. Often these signals are sent or received via defined frequency channels. For selecting a particular frequency channel, the frequency of the LO is typically changed in order to properly transmit or receive the signal via the selected channel. Often a phase locked loop (PLL), such as a digital PLL (DPLL), is used to perform the change in the LO frequency.
A typical DPLL includes several digital devices, such as an input accumulator, a low pass filter (LPF) (often referred to as a “loop filter”), a digital controlled oscillator (DCO), a DCO accumulator, a time-to-digital converter (TDC), and other digital devices. Some of these digital devices use a reference clock to perform their intended function. For example, the input accumulator uses the reference clock to generate a signal indicative of the phase and frequency of an input signal to the DPLL. Also, the DCO accumulator and TDC use the reference clock to generate a signal indicative of the phase and frequency of the output signal of the DCO.
The power consumption of such digital devices is generally proportional or directly related to the frequency of the reference clock. Thus, the DPLL consumes more power when the frequency of the reference clock is relatively high, and less power when the frequency of the reference clock is relatively low. Often, communication devices that employ such DPLLs are portable devices that use limited power supplies, such as a battery, to operate on a continuous basis. In order to extend the continuous operation of such communication devices, it is preferred that the devices be operated in a low power mode whenever possible. One way this can be accomplished is by lowering the frequency of the reference clock when the communication device does not need to operate in a high performance model.
One issue with changing the frequency of the reference clock is that it should be done without significantly affecting the loop control of the DPLL. Prior approaches have been developed that allow for changing the frequency of the reference clock without significantly affect the loop control of the DPLL. However, these approaches typically take a substantial amount of time to perform the frequency change and the relocking operation, which in many applications may not be acceptable.